Dr. Archana Pandey’s research focuses on the design, modeling, and application of novel semiconductor devices and advanced VLSI circuits, with expertise in FinFETs, Gate-All-Around and Nanosheet FETs, Negative Capacitance FETs, Tunnel FETs, and emerging 2D-material-based transistors. Her work combines fundamental device physics with practical circuit co-design to address challenges in low-power, high-performance nanoelectronics. Some of her notable contributions include uncovering voltage transition anomalies in multi-stage FinFET circuits, proposing gate-engineered nanowire FET architectures with enhanced efficiency, developing negative capacitance FinFET gas sensors for improved environmental and biomedical sensing, and advancing self-heating optimization strategies for nanosheet FETs. She has also contributed to AI/ML-driven approaches in VLSI, aiming to integrate predictive analytics with semiconductor design and manufacturing. Dr. Pandey has published extensively in high-impact journals such as IEEE Transactions on Electron Devices, IEEE Sensors Journal, ECS Journal of Solid State Science and Technology, Silicon, and Journal of Electronic Materials, alongside multiple conference papers, book chapters, and a co-edited book “Nanoscale Field Effect Transistors: Emerging Applications” (Bentham, 2023). She actively collaborates with leading institutes including University of Minnesota, IIT Roorkee, IIT Bhilai, and NIT Warangal, while also contributing to executive training programs at JIIT Noida. Her research continues to impact both academia and industry by enabling next-generation device innovations, advancing semiconductor education, and supporting real-world applications in electronics, sensing, and smart technologies.