Dr. Satyendra Kumar at JIIT, Noida, has made significant contributions to the design and simulation of steep subthreshold-slope semiconductor devices, focusing on Tunnel Field-Effect Transistors (TFETs), Negative Capacitance Field-Effect Transistors (NCFETs), and low-power Static Random-Access Memory (SRAM) designs. His research addresses the critical need for energy-efficient devices in ultra-low-power applications by overcoming the limitations of conventional MOSFETs, such as the 60 mV/decade subthreshold swing (SS) limit. Dr. Kumar’s work on TFETs explores novel architectures like dual-material double-gate and stack junction less TFETs, achieving SS below 60 mV/decade and high ON/OFF current ratios (>105) for low-power integrated circuits. His studies incorporate advanced materials and heterostructures, optimizing tunneling efficiency and reducing ambipolarity. For NCFETs, his simulations leverage ferroelectric materials like HfO2 to amplify gate voltage, enabling ultra-steep SS (<40 mV/decade) and improved energy efficiency at sub-0.5V supply voltages. In low-power SRAM design, Dr. Kumar’s innovations include read-SNM-free SRAM cells and TFET-based SRAM, enhancing stability and reducing power consumption in deep submicron technologies. His work on SRAM read and write assist techniques enhances memory performance for low-power applications, critical for energy-efficient electronics. His publications, including works in reputed SCI indexed journals like IEEE transactions, Silicon, Applied Physics-A etc., and IEEE conferences, highlight techniques like metal-strip gate oxide underlap and Gaussian-doped channels to minimize leakage and enhance analog/RF performance. These advancements position his research as pivotal for next-generation IoT and energy-harvesting applications, aligning with the industry’s push for scalable, high-performance, low-power devices.